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NXP Semiconductors
PCA9624
8-bit Fm+ I 2 C-bus 100 mA 40 V LED driver
[2]
[3]
[4]
[5]
[6]
t VD;DAT = minimum time for SDA data out to be valid following SCL LOW.
A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V IL of the SCL signal) in order to
bridge the undefined region of SCL’s falling edge.
The maximum t f for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time (t f ) for the SDA output stage is specified at
250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without
exceeding the maximum specified t f .
C b = total capacitance of one bus line in pF.
Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
SDA
0.7 × V DD
0.3 × V DD
t BUF
t r
t f
t HD;STA
t SP
t LOW
SCL
0.7 × V DD
0.3 × V DD
t HD;STA
t SU;STA
t SU;STO
P
S
t HD;DAT
t HIGH
t SU;DAT
Sr
P
002aaa986
Fig 19. Definition of timing
protocol
START
condition
(S)
bit 7
MSB
(A7)
bit 6
(A6)
bit 1
(D1)
bit 0
(D0)
acknowledge
(A)
STOP
condition
(P)
SCL
t SU;STA
t LOW
t HIG H
1 / f SCL
0.7 × V DD
0.3 × V DD
SDA
t BUF
t r
t f
0.7 × V DD
0.3 × V DD
t HD;STA
t SU;DAT
t HD;DAT
t VD;DAT
t VD;ACK
t SU;STO
002aab285
Rise and fall times refer to V IL and V IH .
Fig 20. I 2 C-bus timing diagram
PCA9624
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 6 September 2012
? NXP B.V. 2012. All rights reserved.
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